1. Field
Present embodiments relate to a semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, along with increasingly high integration of semiconductor memory devices, LSI elements configuring these devices have been more and more miniaturized. This miniaturization of LSI elements requires not only simply that line width be narrowed, but also an improvement in dimensional accuracy, positional accuracy and so on of circuit patterns. An example of a technology that has been proposed for overcoming such problems is ReRAM (Resistive RAM) where a variable resistance element having a reversibly changeable resistance value is employed as a memory cell. Moreover, having this ReRAM adopt a VAL (Vertical Array Line) structure where the variable resistance element is provided between a side wall of a word line extending parallel to a substrate and a side wall of a bit line extending perpendicularly to the substrate enables even higher integration of a memory cell array to be achieved.
However, in the VAL structure, a variable resistance layer functioning as the ReRAM is provided not only on a side surface of the word line, but also on a side surface of an interlayer insulating layer between word lines. Therefore, a leak current occurs between word lines via the variable resistance layer. Moreover, this leak current causes malfunction of memory cells to occur and power consumption to increase.